Nested Paging

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In Computer Platform Virtulisation, Nested Paging is used to unburden the Hypervisor from heavy work with Guest OS memory translation. Before, Hypervisor needs to employ a second page table keeping track of guest page table, and force the guest OS use it to access system physical memory. For doing this, Hypervisor needs to monitor the paging activities of guest OS and intercept it with necessarily inserting, deleting or modifying entries in this second page table. This consumes processor's time and system physical memory space. Nested Paging provides a Second Level Address Translation. With help of it, Hypervisor does not need to maintain that second page table with intercepting activities on guest paging. It simply maintains the nested page table for translating the guest physical address into the system physical address. After nested page table created, the paging hardware does the translation job automatically. Each guest physical access would incur nested paging, for a 48-bit address paging in 4KiB, a guest physical address translation would need 25 accesses of system physical memory. So larger TLB and page size would decrease the system physical memory accesses.


Processors[change | change source]

AMD RVI:

AMD 10h and later

Intel EPT:

Intel Nehalem and later