Von Neumann architecture

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Von Neumann architecture or the von Neumann model is an early computer design description. It was written by mathematician and physicist John von Neumann and others in the First Draft of a Report on the EDVAC.[1]

It describes a design an electronic digital computer with subsections of a processing unit including an arithmetic logic unit, processor registers, a control unit that has the instruction register and program counter, memory to store both data and instructions, and input and output devices.

This means a stored-program computer where the "instruction fetch", the step getting the instruction from memory, and a data operation, the instruction actually happening, cannot be done at the same time because of they use the same bus. This limit is called the von Neumann bottleneck.

Early von Neumann computers[change | change source]

These are some examples of von Neumann model computers.

  • Manchester Mark 1
  • IAS machine

Evolution[change | change source]

Through the 1960's and 1970's computers became smaller and faster, leading to improvements in the design. The is sometimes called "streamlining" the design.

Von Neumann bottleneck[change | change source]

The common bus used by the program memory and data memory creates what is called the von Neumann bottleneck, which is the limit of the data transfer rate between the CPU and memory. Because the program and data cannot be accessed at the same time, the data transfer rate is smaller than the rate the CPU can work, limiting the effective processing speed of the CPU. It is made to wait for the data it needs to be moved to or from memory.

References[change | change source]

  1. von Neumann, John (1945), First Draft of a Report on the EDVAC. [1]