Von Neumann architecture
Von Neumann architecture or the von Neumann model is an early computer design description. It was written by mathematician and physicist John von Neumann and others in the First Draft of a Report on the EDVAC.
It describes a design of an electronic digital computer. There are subsections of a processing unit with an arithmetic logic unit, processor registers, a control unit with an instruction register and program counter, memory to store data and instructions, and input and output devices.
This means a stored-program computer. It has an "instruction fetch", the step getting the instruction from memory, and a data operation, the instruction actually happening. These cannot be done at the same time because they use the same bus. This limit is called the von Neumann bottleneck.
Early von Neumann computers[change | change source]
These are some examples of von Neumann model computers.
- Electronic Delay Storage Automatic Calculator (EDSAC)
- Manchester Mark 1
- IAS machine
- ORACLE (computer)
Evolution[change | change source]
Through the 1960s and 1970s computers became smaller and faster, leading to improvements in the design. This is sometimes called "streamlining" the design.
Von Neumann bottleneck[change | change source]
The common bus used by the program memory and data memory creates what is called the von Neumann bottleneck, which is the limit of the data transfer rate between the CPU and memory. Because the program and data cannot be accessed at the same time, the data transfer rate is smaller than the rate the CPU can work, limiting the effective processing speed of the CPU. It is made to wait for the data it needs to be moved to or from memory.
The Von Neumann bottleneck can be avoided if data and program are transferred on separate buses. This is achieved by the Harvard architecture.
References[change | change source]
- von Neumann, John (1945), First Draft of a Report on the EDVAC. 
- bus = device which transfers data