Reduced instruction set computer
A reduced instruction set computing (acronym RISC pronounced risk), represents a CPU design method to simplify instructions which "do less" but provide higher performance by making instructions execute very fast.
RISC was developed as an alternative to what is now known as CISC. However, there are CPU designs other than RISC and CISC. Some examples are VLIW, MISC, OISC, massive parallel processing, systolic array, reconfigurable computing, and dataflow architecture.
- Instruction level parallelism (ILP) which increases the rate at which instructions are executed within a CPU
- Thread level parallelism (TLP) which increases the number of threads the CPU can execute "in-parallel".
Other features, which are typically found in RISC architectures are:
- Uniform instruction format, using a single word with the opcode in the same bit positions in every instruction, requiring less decoding.
- Similar general purpose registers, allowing any register to be used by any method, simplifying compiler design. However most RISC CPUs have separate floating point registers.
- Simple addressing modes. Complex addressing performed via sequences of arithmetic and/or load-store operations.
- Few data types in hardware. Some CISCs have byte string instructions, or support complex numbers, which are almost never found on a RISC.
Related pages[change | change source]
- Complex instruction set computer
- Very long instruction word
- Minimal instruction set computer
- Zero instruction set computer
- Instruction set architecture
- Computer architecture
Other websites[change | change source]